This article describes a pipeline synthesis and optimization technique that increases data throughput of FPGAbased\r\nsystem using minimum pipeline resources. The technique is applied on CAL dataflow language, and\r\ndesigned based on relations, matrices, and graphs. First, the initial as-soon-as-possible (ASAP) and as-late-aspossible\r\n(ALAP) schedules, and the corresponding mobility of operators are generated. From this, operator coloring\r\ntechnique is used on conflict and nonconflict directed graphs using recursive functions and explicit stack\r\nmechanisms. For each feasible number of pipeline stages, a pipeline schedule with minimum total register width is\r\ntaken as an optimal coloring, which is then automatically transformed to a description in CAL. The generated\r\npipelined CAL descriptions are finally synthesized to hardware description languages for FPGA implementation.\r\nExperimental results of three video processing applications demonstrate up to 3.9Ã?â?? higher throughput for\r\npipelined compared to non-pipelined implementations, and average total pipeline register width reduction of up\r\nto 39.6 and 49.9% between the optimal, and ASAP and ALAP pipeline schedules, respectively.
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